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Senior Formal Verification Engineer at TechBiz Global GmbH

Puesto Senior Formal Verification Engineer
Publicado 11 Jul 2026
Expirado 10 Aug 2026
Empresa TechBiz Global GmbH
Ubicación Barcelona | ES
Tipo de Contrato Full Time

Descripción del Puesto:

Última información laboral de TechBiz Global GmbH para la posición de Senior Formal Verification Engineer. If the Senior Formal Verification Engineer vacante en Barcelona coincide con tus calificaciones, envía tu solicitud o currículum directamente a través del portal actualizado de Jobkos.

Ten en cuenta que aplicar a un trabajo puede no ser siempre fácil, ya que los candidatos deben cumplir con ciertos requisitos establecidos por la empresa. Esperamos que esta oportunidad en TechBiz Global GmbH para la posición de Senior Formal Verification Engineer se ajuste a tu perfil profesional.

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this Puesto, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.


Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

  • End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
  • Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
  • Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
  • RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
  • Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

  • Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
  • SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Información de la Vacante:

  • Empresa: TechBiz Global GmbH
  • Puesto: Senior Formal Verification Engineer
  • Lugar de Trabajo: Barcelona
  • País: ES

Cómo Enviar tu Postulación:

Después de leer y comprender los criterios y requisitos mínimos explicados en la información del trabajo Senior Formal Verification Engineer at the office Barcelona anterior, completa de inmediato tus archivos de solicitud, como carta de presentación, CV (Hoja de Vida), copia de diploma y otros suplementos. Envía a través del enlace Siguiente Página abajo.

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